Verilog help

John_Doe · **Posted:** Tue 03-31-2009 5:43PM

I've been trying to learn how to program a FPGA using verilog for awhile. However, I seem to be having trouble with simple delays and forcing values internally. For example, when I try to simulate the following in Quartus:

Quote:

module top(clk);

output clk;
reg clk;

initial begin
clk = 0;
end

always begin
#15 clk=1;
#15 clk=0;
end

endmodule

the clk signal never changes values (staying at 0). I would appreciate any help.

theshed · **Posted:** Tue 03-31-2009 9:00PM

Not sure, but try this:

Code:

always begin
#15;
clk=1;
#15;
clk=0;
end

As the time delays are statements, them being on the same line as you changing clk's value, there may have been a problem there.
Also, if this loops through, the only thing I see that's output comes after clk has been changed from 1 back to 0.

And as I've never seen or heard of this language before tonight, theres a pretty good chance that this is all completely off and wrong.

John_Doe · **Posted:** Wed 04-01-2009 4:46PM

Figured it out....Quartus actually only supports a subset of the Verilog language and timing delays is one of the features that isn't supported.

Verilog help

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